Implementation of Compaction Algorithm for ATPG Generated Partially Specified Test Data

n this paper the ATPG is implemented using C++. This ATPG is based on fault equivalence concept inwhich the number of faults gets reduced before compaction method. This ATPG uses the line justificationand error propagation to find the test vectors forreduced fault set with the aid of controllability andobservability. Single stuck at fault model is considered. The programs are developed for fault equivalencemethod, controllability Observability, automatic test pattern generation and test data compaction usingobject oriented language C++. ISCAS 85 C17 circuitwas used for analysis purpose along with othercircuits. Standard ISCAS (International Symposium on Circuits And Systems) netlist format was used. Theflow charts and results for ISCAS 85 C17 circuits along with other netlists are given in this paper. The testvectors generated by the ATPG further compacted toreduce the test vector data. The algorithm isdeveloped for the test vector compaction and discussed along with result