Exploring Alternative Topologies for Network-on-Chip Architectures

With increase in integration density and complexity of the system-on-Chip (SOC), the conventional interconnects are not suitable to fulfill the demands. The application of traditional network technologies in the form of Network-on-Chip is a potential solution. NoC design space has many variables. Selection of a better topology results in lesser complexities and better power-efficiency. In the proposed work, key research area in Network-on-chip design targeting communication infrastructure specially focusing on optimized topology design is worked upon. The simulation is modeled using a conventional network simulator tool packet tracer 5.3, in which by selecting proposed Topology 35.7 % reduction in traversing the longest path is observed.