The current trend of digital convergence leads to the need of the video encoder/decoder (codec) that should support multiple video standards on a single platform as it is expensive to use dedicated video codec chip for each standard. The paper presents a high performance circuit shared architecture that can perform the quantization of five popular video codecs such as H.264/AVC, AVS, VC-1, MPEG-2/4, and JPEG. The proposed quantizer architecture is completely division-free as the division operation is replaced by shift and addition operations for all the standards. The design is implemented on FPGA and later synthesized in CMOS 0.18？ m technology. The results show that the proposed design satisfies the requirement of all five codecs with a maximum decoding capability of 60？fps at 187？MHz on Xilinx FPGA platform for 1080？p HD video. 1. Introduction An evident trend in modern world is the digital convergence in the current electronic consumer products. People want the portable devices to have various functions like Video on Demand (VOD), Digital Multimedia Broadcasting (DMB), Global Positioning System (GPS) or the navigation system, Portable Multimedia Player (PMP), and so on. Due to such demand, it is necessary to support the widely used video compression standards in a single system-on-chip (SoC) platform. So the goal is to find a way so that the multicodec system achieves high performance, as well as low cost. Most modern multimedia codecs (both encoder and decoder) employ transform-quantization pair as shown in Figure 1. A significant research has been conducted to combine and efficiently implement the transform units for multiple codecs, but little research is focused on the implementation of multiquantizer unit. A unified Inverse Discrete Cosine Transform (IDCT) architecture to support five standards (such as, AVS, H.264, VC-1, MPEG-2/4, and JPEG) is presented in [1]. A design to support the 4 × 4 transform and quantization of H.264 has been presented in [2]. The 8 × 8 transform and quantization for H.264 is presented in [3] and [4]. Several other designs based on H.264 codec have been reported in [5–10]. The authors in [11] present a design for the quantization for AVS. The design in [12] describes an MPEG-2 encoder. In [13], another JPEG encoder is implemented for images where the quantization block is designed using multiplication and shift operation instead of division. The design in [14] describes a multistandard video decoder to support four codecs—AVS, H.264, VC-1, and MPEG-2. Silicon Image Inc. currently supplies a Multi-standard
References
[1]
K. A. Wahid, M. Martuza, M. Das, and C. McCrosky, “Efficient hardware implementation of 8x8 integer cosine transforms for multiple video codecs,” Journal of Real-Time Image Processing. In press.
[2]
R. C. Kordasiewicz and S. Shirani, “ASIC and FPGA implementations of H.264 DCT and quantization blocks,” in Proceedings of the IEEE International Conference on Image Processing (ICIP '05), pp. 1020–1023, September 2005.
[3]
S. P. Jeoong and T. Ogunfunmi, “A new hardware implementation of the H.264 8x8 transform and quantization,” in Proceedings of the IEEE International Conference on Acoustics, Speech, and Signal Processing (ICASSP '09), pp. 585–588, April 2009.
[4]
I. Amer, W. Badawy, and G. Jullien, “A high-performance hardware implementation of the H.264 simplified 8x8 transformation and quantization,” in Proceedings of the IEEE International Conference on Acoustics, Speech, and Signal Processing (ICASSP '05), pp. II1137–II1140, March 2005.
[5]
G. Pastuszak, “Transforms and quantization in the high-throughput H.264/AVC encoder based on advanced mode selection,” in Proceedings of the IEEE Computer Society Annual Symposium on VLSI: Trends in VLSI Technology and Design (ISVLSI '08), pp. 203–208, April 2008.
[6]
X. T. Tran and V. H. Tran, “Cost-efficient 130nm TSMC forward transform and quantization for H.264/AVC encoders,” in Proceedings of the 14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS '11), pp. 47–52, April 2011.
[7]
R. Husemann, M. Majolo, V. Guimaraes, A. Susin, V. Roesler, and J. V. Lima, “Hardware integrated quantization solution for improvement of computational H.264 encoder module,” in Proceedings of the 18th IEEE/IFIP International Conference on VLSI and System-on-Chip (VLSI-SoC '10), pp. 316–321, September 2010.
[8]
R. Kordasiewicz and S. Shirani, “Hardware implementation of the optimized transform and quantization blocks of H.264,” in Proceedings of the Canadian Conference on Electrical and Computer Engineering (CCECE '04), vol. 2, pp. 0943–0946, May 2004.
[9]
O. Tasdizen and I. Hamzaoglu, “A high performance and low cost hardware architecture for H. 264 transform and quantization algorithms,” in Proceedings of the 13th European Signal Processing Conference, pp. 4–8, September 2005.
[10]
C. P. Fan and Y. L. Cheng, “FPGA implementations of low latency and high throughput 4x4 block texture coding processor for H.264/AVC,” Journal of the Chinese Institute of Engineers, vol. 32, no. 1, pp. 33–44, 2009.
[11]
K. Zhang, Y. Zhu, and L. Yu, “Area-efficient quantization architecture with zero-prediction method for AVS encoders,” in Proceedings of the Picture Coding Symposium (PCS '07), p. 4, November 2007.
[12]
K. Suh, K. Y. Min, K. Kim, J. S. Koh, and J. W. Chong, “Design of DPCM hybrid coding loop using single 1-D DCT in MPEG-2 video encoder,” in Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS '99), pp. V-279–V-282, June 1999.
[13]
H. Osman, W. Mahjoup, A. Nabih, and G. M. Aly, “JPEG encoder for low-cost FPGAs,” in Proceedings of the International Conference on Computer Engineering and Systems (ICCES '07), pp. 406–411, November 2007.
[14]
C. C. Ju, Y. C. Chang, C. Y. Cheng et al., “A full-HD 60fps AVS/H.264/VC-1/MPEG-2 video decoder for digital home applications,” in Proceedings of the International Symposium on VLSI Design, Automation and Test (VLSI-DAT '11), pp. 1–4, April 2011.
CCITT recommendation T. 81, digital compression and coding continuous-tone still images, 1992.
[17]
ISO/IEC, Information technology—generic coding of moving pictures and associated audio information: video, 13818-2:1995.
[18]
Standard for television: VC-1 compressed video bitstream format and decoding process, SMPTE 421 M, 2006.
[19]
ITU-T Rec. H. 264/ISO/IEC, 14496-10 AVC, 2003.
[20]
GB/T, 20090. 1 Information technology—advanced coding of audio and video Part 1: system, Chinese AVS standard.
[21]
S. Srinivasan, P. Hsu, T. Holcomb et al., “Windows media video 9: overview and applications,” Signal Processing, vol. 19, no. 9, pp. 851–875, 2004.
[22]
A. Vetro, C. Christopoulos, and H. Sun, “Video transcoding architectures and techniques: an overview,” IEEE Signal Processing Magazine, vol. 20, no. 2, pp. 18–29, 2003.
[23]
I. Ahmad, X. Wei, Y. Sun, and Y. Q. Zhang, “Video transcoding: an overview of various techniques and research issues,” IEEE Transactions on Multimedia, vol. 7, no. 5, pp. 793–804, 2005.
[24]
C. J. Lian, L. G. Chen, H. C. Chang, and Y. C. Chang, “Design and implementation of JPEG encoder IP core,” in Proceedings of the Asia and South Pacific Design Automation Conference, pp. 29–30, 2001.
[25]
L. Yu, F. Yi, J. Bong, and C. Zhang, “Overview of AVS-video: tools, performance and complexity,” in Visual Communications and Image Processing, vol. 5960 of Proceedings of SPIE, pp. 679–690, July 2005.
[26]
J. B. Lee and H. Kalva, The VC-1 and H.264 Video Compression Standards for Broadband Video Services, vol. 32, Springer, Florida, Fla, UDA, 1st edition, 2008.
