An improved physics-based compact model for a symmetrically biased gate-all-around (GAA) silicon nanowire transistor is proposed. Short channel effects and quantum mechanical effects caused by the ultrathin silicon devices are considered in modelling the threshold voltage. Device geometrics play a very important role in multigate devices, and hence their impact on the threshold voltage is also analyzed by varying the height and width of silicon channel. The inversion charge and electrical potential distribution along the channel are expressed in their closed forms. The proposed model shows excellent accuracy with TCAD simulations of the device in the weak inversion regime. 1. Introduction Semiconductor nanowires are attractive components for future nanoelectronics since they can exhibit a wide range of device function and at the same time serve as bridging wires that connect larger scale metallization. The nanoscale FETs based on silicon nanowires have notable attention for their potential applications in electronics industry. In a continuous effort to increase current drive and better control over SCEs, silicon-on-insulator (SOI) MOS transistors have evolved from classical, planar, and single-gate devices into 3D devices with a multigate structure (double-, triple-, or gate-all-around devices). These multigate nanowire FETs that prevent the electric field lines from originating at the drain from terminating under the channel region are now widely recognized as one of the most auspicious solutions, for meeting the roadmap requirements in the decananometer scale. Multigate device structures of nanowire transistors pave the way for better electrostatic control, and as a result, intrinsic channels get higher mobility and current [1]. CMOS devices can be scaled down up to a channel length of 10？nm when the number of gates in the device is increased. In such transistors the short channel effects are controlled by the device geometry, and hence an undoped or lightly doped ultrathin body is used to sustain the channel. Various device structures such as double gate fully depleted SOI, trigate, and all around gate structures have been extensively investigated to restrict SCEs within a limit while achieving the primary advantages of scaling, that is, higher performance, lower power, and ever increasing integration density [2]. The scaling theory and the analytical SCEs model for nanowire transistors based on the concept of natural length are successful to a certain extent. To address the issue of 2D effects in the gate insulator, a more generalized concept of
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