An Inductorless Cascaded Phase-Locked Loop with Pulse Injection Locking Technique in 90？nm CMOS

An inductorless phase-locked loop with subharmonic pulse injection locking was realized (PLL area: 0.11？mm2) by adopting 90？nm Si CMOS technology. The proposed circuit is configured with two cascaded PLLs; one of them is a reference PLL that generates reference signals to the other one from low-frequency external reference signals. The other is a main PLL that generates high-frequency output signals. A high-frequency half-integral subharmonic locking technique was used to decrease the phase noise characteristics. For a 50 MHz input reference signal, without injection locking, the 1 MHz offset phase noise was ？88？dBc/Hz at a PLL output frequency of 7.2？GHz (= 144 × 50？MHz); with injection locking, the noise was ？101？dBc/Hz (spur level: ？31？dBc; power consumption from a 1.0？V power supply: 25？mW). 1. Introduction Conventional multistandard wireless mobile terminals contain multiple RFICs. To reduce production costs, one-chip wideband RF LSI systems are desired. A great effort is being made to develop wideband and/or multiband RF solutions using highly scaled advanced CMOS processes. The use of such processes is beneficial to and converters and digital baseband circuits. However, it is very difficult to reduce the scale of RF/analog circuit blocks, especially power amplifiers and oscillator circuits, including voltage-controlled oscillators (VCOs) and phase-locked loops (PLLs), because of the presence of inductors that do not scale with advancements in technology. In designing VCOs which generate signals in RF systems, ring-type VCOs (ring VCOs) are more attractive than LC-resonant-type VCOs (LC VCOs) in terms of their small area and wide frequency tuning range since they do not use large passive devices. However, they have poor phase noise with relatively high power consumption. Nevertheless, low-phase-noise ring VCO is still a possibility if some noise-suppression mechanism is applied. One of available options would be injection locking. In the early days, Adler [1] and many other authors studied the behavior of VCOs with injection locking. Also, there are numerous papers published in reference to VCOs with injection locking in order to achieve phase locking and high performances. Moreover, recently, PLLs with an injection-locked frequency divider and frequency multiplier, and a clock and data recovery circuit (CDR) were presented. This paper describes a study on a ring-VCO-based PLL with pulse injection locking as a potential solution to realize a scalable inductorless PLL, which can generate wideband frequency signal with low supply voltage. Usually,