Low-Jitter 0.1-to-5.8？GHz Clock Synthesizer for Area-Efficient Per-Port Integration

Phase-locked loops (PLLs) employing LC-based voltage-controlled oscillators (LC VCOs) are attractive in low-jitter multigigahertz applications. However, inductors occupy large silicon area, and moreover dense integration of multiple LC VCOs presents the challenge of electromagnetic coupling amongst them, which can compromise their superior jitter performance. This paper presents an analytical model to study the effect of coupling between adjacent LC VCOs when operating in a plesiochronous manner. Based on this study, a low-jitter highly packable clock synthesizer unit (CSU) supporting a continuous (gapless) frequency range up to 5.8？GHz is designed and implemented in a 65？nm digital CMOS process. Measurement results are presented for densely integrated CSUs within a multirate multiprotocol system-on-chip PHY device. 1. Introduction The design of clock multipliers for multirate multistandard applications involves a tradeoff between the output clock jitter and the frequency tuning range. Traditionally, a wide range is achieved via non-LC-based oscillators such as relaxation or ring oscillators [1–3] at the cost of higher phase noise and intrinsic jitter. LC VCOs are used for low-jitter multigigahertz applications, but their tuning range is inherently small [2, 4]. Moreover, dense integration of multiple LC VCOs on a silicon die poses a new challenge due to mutual coupling between inductors and the resulting frequency pulling and induced phase jitter among adjacent oscillators. In this work, a low-jitter highly packable Clock-Synthesizer Unit (CSU) supporting a continuous (gapless) frequency range up to 5.8？GHz is designed and implemented in 65？nm digital CMOS process. One of the objectives of this clock generation architecture is to close the gap between ring oscillators with wide tuning range but high phase-noise and jitter and LC oscillators with limited tuning range and low phase noise. The clock synthesizer architecture is described in Section 2. In Section 3, a model is presented that describes the effect of magnetic coupling between adjacent VCOs and the resulting phase jitter in the PLL under test. Implementation results and conclusions are presented in Sections 4 and 5, respectively. 2. Architecture The clock synthesizer unit presented in this work is intended for per-port integration in transceivers supporting various wireline telecommunications and data communication standards. As shown in Figure 1, the CSU receives a stable crystal-based reference clock (REFCLK) and employs two LC VCOs, a programmable charge pump, a high-speed fractional