Long channel carbon nanotube transistor (CNT) can be used to overcome the high electric field effects in nanoscale length silicon channel. When maximum electric field is reduced, the gate of a field-effect transistor (FET) is able to gain control of the channel at varying drain bias. The device performance of a zigzag CNTFET with the same unit area as a nanoscale silicon metal-oxide semiconductor field-effect transistor (MOSFET) channel is assessed qualitatively. The drain characteristic of CNTFET and MOSFET device models as well as fabricated CNTFET device are explored over a wide range of drain and gate biases. The results obtained show that long channel nanotubes can significantly reduce the drain-induced barrier lowering (DIBL) effects in silicon MOSFET while sustaining the same unit area at higher current density. 1. Introduction Carbon nanotubes (CNTs) are gaining momentum in the current silicon technology as a complementary nanostructure that could reform the device architecture. CNT modeling has been rigorously studied and examined [1–5] to assess the performance of the device at the circuit level. Advancement of the nanotechnology devices modeling is vital for the foreseeable future of carbon nanotube as switching device, interconnect and memory in integrated circuits (ICs). An in situ growth single-walled carbon nanotube (SWCNT), which integrates long channel 600？nm CNT channel, thin Al2O3 top gate contact, and Palladium (Pd) metal source/drain contacts, has been demonstrated [6]. In addition, we report the potential of long channel 65？nm CNT as substitute to 45？nm silicon metal-oxide semiconductor field-effect transistor (Si MOSFET) from the perspective of modeling for future CNT-logic applications. We observe good agreement between CNTFET and Si MOSFET, respectively, when simulating two-terminal drain current–voltage ( ) characteristic. The projection has shed light on the reduction of DIBL and high field effects [7] as well as reduction in long channel CNT which is a widespread phenomenon in nanoscale Si MOSFET [8, 9]. We also demonstrate the effects of the channel area restructuring on the maximum electric field as well as density of states (DOS) in the conductance of CNT. Unlike MOSFET, it is revealed that the performance of CNT is enhanced when the source and drain width is minimized rather than the length, primarily due to the gate-to-source-drain parasitic fringe capacitances [10]. MOSFET scaling in accordance with Moore’s Law will reach its fundamental limitation as a result of process controllability in the next 10 years.
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