Pulse Edge-Only Signaling Method Comparison for Wireline Interconnects

Typical high-speed electrical transmission lines use a variety of precoding and equalization techniques to counter the frequency-dependent channel loss and environmental conditions such as ISI. In this paper, we suggest a relatively narrow-band signaling method that is resilient to the effects of ISI and crosstalk and can be implemented with existing technology. Alternative modulation schemes are analyzed in terms of effectiveness, performance, and cost. In particular, line-encoded and on-off keyed modulation methods are evaluated in simulations of transmission lines to gauge effectiveness in high-speed conditions with limiting ISI. 1. Introduction Modern digital communications across transmission lines have long been analyzed for methods to generate and transmit binary signals at high speeds. The most popular technique is to transmit using the non-return-to-zero (NRZ) line code modulation scheme and subsequently use a variety of channel equalization methods to counteract channel distortions such as intersymbol interference (ISI) [1, 2]. Such equalization methods, most recently, were focused on adaptive filter design to cancel out the channel effects estimated via, for example, time-domain reflectometry (by evaluating channel’s impulse response). In [3] the authors suggest generating error terms derived from the channel’s impulse response to be used in equalizing filter which minimizes ISI accumulation. The method showed promise in simulations up to 20？Gb/s over 6-in wireline channels. Another filter-based method described in [4] specifically addresses the problem of delay line usage in such systems, which are prone to process, voltage, and temperature variations. By proposing an active delay line the authors claim improvement over these shortcomings and demonstrate the experimental performance at 10？Gb/s over 20 in interconnect. The system required four buffers used as delay line components and four buffers used as amplifiers. Simulation study of another FIR-based equalizer in [5] used 7-tap delay line model with passive LC components, which would require significant chip area for implementation. FIR equalizers implemented in GaAs HBT and 0.18？um CMOS to achieve 5？Gb/s over 26 in FR4 backplane with active NEXT cancellation (also via FIR implementation) are described in [6]. The overview of passive and active equalization methods is also given in [7]. These are fairly complex equalization methods which tend to increase the device power consumption, reduce compatibility with other devices (via, e.g., increasing crosstalk if high-frequency components of