Design of Low Power and Efficient Carry Select Adder Using 3-T XOR Gate

In digital systems, mostly adder lies in the critical path that affects the overall performance of the system. To perform fast addition operation at low cost, carry select adder (CSLA) is the most suitable among conventional adder structures. In this paper, a 3-T XOR gate is used to design an 8-bit CSLA as XOR gates are the essential blocks in designing higher bit adders. The proposed CSLA has reduced transistor count and has lesser power consumption as well as power-delay product (PDP) as compared to regular CSLA and modified CSLA. 1. Introduction In today’s VLSI circuit designs, there is a significant increase in the power consumption due to the increasing speed and complexity of the circuits. As the demand for portable equipment like laptops and cellular phones is increasing rapidly, great attention has been focused on power efficient circuit designs [1–4]. Adders are the basic building blocks of the complex arithmetic circuits. Adders are widely used in Central Processing Unit (CPU), Arithmetic Logic Unit (ALU), and floating point units, for address generation in case of cache or memory access and in digital signal processing [5–7]. Having adders with fast addition operation and low power along with low area consumption is still a challenging issue. Depending upon the area, delay, and power consumption, the various adders are categorized as ripple carry adder (RCA), carry select adder (CSLA), and carry lookahead adder (CLAA). CSLA provides a compromise between the large area with small delay of CLAA and small area but longer delay of RCA [8]. CSLA uses pair of RCAs for addition, that is, one block of RCA with (carry in) = 0 and other block of RCA with = 1. Depending on the value of previous carry, the final sum and carry outputs are selected using multiplexer. Due to the pair of RCAs used for each bit addition, the simplest kind of CSLA is not very efficient [9]. Keeping in mind that XOR gates are the building blocks of adders, here in this work, we use a 3T-XOR gate to design an 8-bit CSLA. The main advantage of using 3T-XOR gate is that the power consumption of the circuit decreases due to the large decrease in number of switching transistors (MOSFETs) used in the design of 8-bit CSLA. This paper is organized as follows. Section 2 presents the earlier works on carry select adder including the detailed structure of regular CSLA as well as modified CSLA. Section 3 explains the proposed CSLA and evaluates the reduction in switching transistors (MOSFETs) count. The implementation details as well as simulation results of proposed CSLA are analyzed in