This paper presents research on a low power CMOS UWB LNA based on a
cascoded common source and current-reused topology. A systematic approach for
the design procedure from narrow band to UWB is developed and discussed in
detail. The power reduction can be achieved by using body biased technique and
current-reused topology. The optimum width of the major transistor device M1 is determined by the
power-constraint noise optimization with inner parasitic capacitance between the
gate and source terminal. The derivation of the signal amplification S21 by high frequency small signal model is displayed in the paper. The optimum
design of the complete circuit was studied in a step by step analysis. The
measurements results show that the proposed circuit has superior S11,
gain, noise figure, and power consumption. From the measured results, S11 is lower than -12 dB, S22 is lower than -10 dB and forward gain S21 has an average value with 12 dB. The noise figure is from 4 to 5.7 dB within
the whole band. The total power consumption of the proposed circuit including
the output buffer is 4.6 mW with a supply voltage of 1 V. This work is
implemented in a standard TSMC 0.18 μm CMOS process technology.
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