An FPGA-based Linux test-bed was constructed for the purpose of measuring its sensitivity to single-event upsets. The test-bed consists of two ML410 Xilinx development boards connected using a 124-pin custom connector board. The Design Under Test (DUT) consists of the “hard core” PowerPC, running the Linux OS and several peripherals implemented in “soft” (programmable) logic. Faults were injected via the Internal Configuration Access Port (ICAP). The experiments performed here demonstrate that the Linux-based system was sensitive to 199,584 or about 1.4 percent of all tested bits. Each sensitive bit in the bit-stream is mapped to the resource and user-module to which it configures. A density metric for comparing the reliability of modules within the system is presented. Using this density metric, we found that the most sensitive user module in the design was the PowerPC's direct connections to the DDR2 memory controller. 1. Introduction Over the last decade, Linux Operating Systems (OSs) have been used on several space-based computing platforms. NASA, for example, sponsored the FlightLinux project which culminated by demonstrating a reliable Linux OS on the UoSat12 satellite [1]. The use of Linux on the UoSat12 provided enough compatibility with ground systems to allow the satellite to be accessible over the Internet. Compatibility with ground systems is only one of the many reasons to use Linux on space-based computing platforms. Reliable hardware is essential for Linux to operate; however, integrated circuits (ICs) aboard space-based computing platforms are susceptible to failures known as Single-Event Upsets (SEUs). SEUs are random bit flips caused by high-energy particles that collide with the ICs. To ensure correct operation in the presence of radiation, ICs can be specially designed or “hardened.’’ Unfortunately, radiation-hardened ICs are expensive and usually two or three silicon generations behind the state of the art [2]. These factors limit the use of radiation-hardened parts in space-based computing and leave engineers looking for alternatives. Field Programmable Gate Arrays (FPGAs) are among the state-of-the-art components that are of interest in space-based computing. FPGAs are microchips that contain an array of logic and interconnect that can be programmed and reprogrammed to perform almost any digital function. FPGAs often replace application-specific integrated circuits (ASICs) in space-based computing because designing for FPGAs is faster and less expensive than designing for ASICs. Additionally, reprogrammability allows designers to
References
[1]
B. Ramesh, T. Bretschneider, and I. Mcloughlin, “Embedded linux platform for a fault tolerant space based parallel computer,” in Proceedings of the Real-Time Linux Workshop, pp. 39–46, 2004.
[2]
D. S. Katz, “Application-based fault tolerance for spaceborne applications,” 2004, http://hdl.handle.net/2014/10574.
[3]
M. Caffrey, “A space-based reconfigurable radio,” in Proceedings of the International Conference on Engineering of Reconfigurable Systems and Algorithms (ERSA '02), T. P. Plaks and P. M. Athanas, Eds., pp. 49–53, CSREA Press, June 2002.
[4]
M. Caffrey, K. Morgan, D. Roussel-Dupre et al., “On-orbit flight results from the reconfigurable cibola flight experiment satellite (CFESat),” in Proceedings of the 17th IEEE Symposium on Field Programmable Custom Computing Machines (FCCM ’09), pp. 3–10, April 2009.
[5]
M. Caffrey, K. Katko, and A. Nelson, “The cibola flight experiment,” in Proceedings of the 23rd Annual Small Satellite Conference, August 2009.
[6]
C. Carmichael, M. Caffrey, and A. Salazar, “Correcting single-event upsets through virtex partial configuration,” Xilinx Application Notes, vol. 1.0, 2000.
[7]
F. L. Kastensmidt, L. Sterpone, L. Carro, and M. S. Reorda, “On the optimal design of triple modular redundancy logic for sram-based fpgas,” in Proceedings of the Conference on Design, Automation and Test in Europe (DATE ’05), pp. 1290–1295, IEEE Computer Society, Washington, DC, USA, 2005.
[8]
S. Baloch, T. Arslan, and A. Stoica, ““Probability based partial triple modular redundancy technique for reconfigurable architectures,” in Proceedings of the IEEE Aerospace Conference, p. 7, 2006.
[9]
D. L. McMurtrey, Using deplication with compare for on-line error detection in FPGA-based designs, Ph.D. dissertation, Brigham Young University, Provo, Utah, USA, 2006.
[10]
F. Lima, C. Carmichael, J. Fabula, R. Padovani, and R. Reis, “A fault injection analysis of virtex fpga tmr design methodology,” in Proceedings of the 6th European Conference on Radiation and Its Effects on Components and Systems, pp. 275–282, 2001.
[11]
J. Monson, M. Wirthlin, and B. Hutchings, “Fault injection results of linux operating on an fpga embedded platform,” in Proceedings of the International Conference on Reconfigurable Computing and FPGAs, pp. 37–42, 2010.
[12]
U. Legat, A. Biasizzo, and F. Novak, “Automated SEU fault emulation using partial FPGA reconfiguration,” in Proceedings of the 13th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS '10), pp. 24–27, 2010.
[13]
M. S. Reorda, L. Sterpone, M. Violante, M. Portela-Garcia, C. Lopez-Ongil, and L. Entrena, “Fault injection-based reliability evaluation of SoPCs,” in Proceedings of the 11th IEEE European Test Symposium (ETS ’06), pp. 75–82, 2006.
[14]
P. Civera, L. Macchiarulo, M. Rebaudengo, M. S. Reorda, and M. Violante, “FPGA-based fault injection for microprocessor systems,” in Proceedings of the 10th Asian Test Symposium, pp. 304–309, November 2001.
[15]
L. Sterpone and M. Violante, “An analysis of SEU effects in embedded operating systems for Real-Time applications,” in Proceedings of the IEEE International Symposium on Industrial Electronics (ISIE '07), pp. 3345–3349, 2007.
[16]
E. Johnson, M. Caffrey, P. Graham, N. Rollins, and M. Wirthlin, “Accelerator validation of an FPGA SEU simulator,” IEEE Transactions on Nuclear Science, vol. 50, no. 6 I, pp. 2147–2157, 2003.
[17]
L. Sterpone and M. Violante, “Static and dynamic analysis of SEU effects in SRAM-based FPGAs,” in Proceedings of the 12th IEEE European Test Symposium (ETS '07), pp. 159–164, May 2007.
[18]
L. Sterpone and M. Violante, “A new analytical approach to estimate the effects of SEUs in TMR architectures implemented through SRAM-based FPGAs,” IEEE Transactions on Nuclear Science, vol. 52, no. 6, pp. 2217–2223, 2005.
[19]
C. Lavin, M. Padilla, J. Lamprecht, P. Lundrigan, B. Nelson, and B. Hutchings, “HMFlow: accelerating FPGA compilation with hard macros for rapid prototyping,” in Proceedings of the 19th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM '11), May 2011.
[20]
G. Allen, “Virtex-4VQ dynamic and mitigated single event upset characterization summary,” 2009, http://hdl.handle.net/2014/41104.
[21]
C. Beckhoff, D. Koch, and J. Torresen, “Short-circuits on fpgas caused by partial runtime reconfiguration,” in Proceedings of the International Conference on Field Programmable Logic and Applications (FPL '10), pp. 596–601, 2010.
[22]
S. Srinivasan, A. Gayasen, and N. Vijaykrishnan, “Leakage control in FPGA routing fabric,” in Proceedings of Conference on Asia South Pacific Design Automation (ASP-DAC'05), vol. 1, pp. 661–664z, 2005.
