One of the most important steps in spectral analysis is filtering, where window functions are generally used to design filters. In this paper, we modify the existing architecture for realizing the window functions using CORDIC processor. Firstly, we modify the conventional CORDIC algorithm to reduce its latency and area. The proposed CORDIC algorithm is completely scale-free for the range of convergence that spans the entire coordinate space. Secondly, we realize the window functions using a single CORDIC processor as against two serially connected CORDIC processors in existing technique, thus optimizing it for area and latency. The linear CORDIC processor is replaced by a shift-add network which drastically reduces the number of pipelining stages required in the existing design. The proposed design on an average requires approximately 64% less pipeline stages and saves up to 44.2% area. Currently, the processor is designed to implement Blackman windowing architecture, which with slight modifications can be extended to other widow functions as well. The details of the proposed architecture are discussed in the paper. 1. Introduction Window filtering techniques [1, 2] are commonly employed in signal processing paradigm to limit time and frequency resolution. Various window functions are developed to suit different requirements for side-lobe minimization, dynamic range, and so forth. Commonly, many hardware efficient architectures are available for realizing FFT [3–5], but the same is not true for windowing–architectures. The conventional hardware implementation of window functions uses lookup tables which give rise to various area and time complexities with increase in word lengths. Moreover, they do not allow user-defined variations in the window length. An efficient implementation of flexible and reconfigurable window functions using CORDIC algorithm is suggested in [6, 7]. Though they allow user-defined variations in window length, latency is a major problem. The CORDIC algorithm [8–10] inherently suffers from latency issues and using two CORDIC processors in series, as is done in [6, 7]; the overall latency of the system is hampered. In this paper, a new area-time efficient FPGA implementation to realize Blackman window function is suggested. We first redesign the conventional CORDIC algorithm to eliminate scale-factor compensation network and optimize its microrotation sequence identification. We then replace the linear CORDIC processors used in the existing design by shift-add tree derived using Booth multiplication. These modifications scale down
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