Massively parallel reconfigurable architectures, which offer massive parallelism coupled with the capability of undergoing run-time reconfiguration, are gaining attention in order to meet the increased computational demands of high-performance embedded systems. We propose that the language is used for programming of the category of massively parallel reconfigurable architectures. The salient properties of the language are explicit concurrency with built-in mechanisms for interprocessor communication, provision for expressing dynamic parallelism, support for the expression of dynamic reconfigurations, and placement attributes. To evaluate the programming approach, a compiler framework was extended to support the language extensions in the language and a backend was developed to target the Ambric array of processors. We present two case-studies; DCT implementation exploiting the reconfigurability feature of and a significantly large autofocus criterion calculation based on the dynamic parallelism capability of the language. The results of the implemented case studies suggest that the -language-based approach simplifies the development of applications employing run-time reconfigurable devices without compromising the performance benefits. 1. Introduction and Motivation The computational requirements of high-performance embedded applications, such as video processing in HDTV, baseband processing in telecommunication systems, and radar signal processing, have reached a level where they cannot be met with traditional computing systems based on general-purpose digital signal processors. Massively parallel reconfigurable processor arrays are made up of highly optimized functional blocks or even program-controlled processing elements composed in a reconfigurable interconnect. The coarse-grained composition leads to less reconfiguration data than in their more fine-grained counterparts, which improves the reconfiguration time, while the communication overhead is also decreased. The ability of coarse-grained reconfigurable architectures to undergo partial and run-time reconfiguration makes them suitable for implementing hardware acceleration of streaming applications. However, developing applications that employ such architectures poses several other challenging tasks. The procedural models of high-level programming languages, such as C, rely on sequential control flow, procedures, and recursion, which are difficult to adapt for reconfigurable arrays. The focus of these sequential languages is to provide abstractions for algorithm specification, but the
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