This paper describes a novel energy-efficient, high-speed ADC architecture combining a flash ADC and a TDC. A high conversion rate can be obtained owing to the flash coarse ADC, and low-power dissipation can be attained using the TDC as a fine ADC. Moreover, a capacitive coupled ramp circuit is proposed to achieve high linearity. A test chip was fabricated using 65-nm digital CMOS technology. The test chip demonstrated a high sampling frequency of 500 MHz and a low-power dissipation of 2.0 mW, resulting in a low FOM of 32 fJ/conversion-step.
References
[1]
Nakura, T., Mandai, S., Ikeda, M. and Asada, K. (2009) Time Difference Amplifier Using Closed-Loop Gain Control. IEEE International Symposium on VLSI Circuits, Kyoto, 16-18 June 2009, 208-209.
[2]
Seo, Y.-H., Kim, J.-S., Park, H.-J. and Sim, J.-Y. (2012) A 1.25 ps Resolution 8b Cyclic TDCin 0.13 μm CMOS. IEEE Journal of Solid-State Circuits, 47, 736-743.
https://doi.org/10.1109/JSSC.2011.2176609
[3]
Kim, K., Yu, W. and Cho, S. (2014) A 9 Bit, 1.12 ps Resolution 2.5 b/Stage Pipelined Time-to-Digital Converter in 65 nm CMOS Using Time-Register. IEEE Journal of Solid-State Circuits, 49, 1007-1016. https://doi.org/10.1109/JSSC.2013.2297412
[4]
Kim, J., Jang, T.-K., Yoon, Y.-G. and Cho, S. (2010) Analysis and Design of Voltage-Controlled Oscillator Based Analog-to-Digital Converter. IEEE Transaction on Circuits and Systems I, 57, 18-30. https://doi.org/10.1109/TCSI.2009.2018928
[5]
Xing, X. and Gielen, G.G.E. (2015) A 42 fJ/Step-FoM Two-Step VCO-Based Delta-Sigma ADC in 40 nm CMOS. IEEE Journal of Solid-State Circuits, 50, 714-723.
https://doi.org/10.1109/JSSC.2015.2393814
[6]
Macpherson, A.R., Haslett, J.W. and Belostotski, L. (2013) A 5GS/s 4-bit Time-Based Single-Channel CMOS ADC for Radio Astronomy. IEEE Custom Integrated Circuits Conference, San Jose, 22-25 September 2013, 1-4.
https://doi.org/10.1109/cicc.2013.6658551
[7]
Zhu, S., Xu, B., Wu, B., Soppimath, K. and Chiu, Y. (2016) A Skew-Free 10 GS/s 6 bit CMOS ADC with Compact Time-Domain Signal Folding and Inherent DEM. IEEE Journal of Solid-State Circuits, 51, 1785-1796.
https://doi.org/10.1109/JSSC.2016.2558487
[8]
Chen, Y.-J., Chang, K.-H. and Hsieh, C.-C. (2016) A 2.02-5.16 fJ/Conversion Step 10 Bit Hybrid Coarse-Fine SAR ADC with Time-Domain Quantizer in 90 nm CMOS. IEEE Journal of Solid-State Circuits, 51, 357-364.
https://doi.org/10.1109/JSSC.2015.2492781
[9]
Oh, T., Venkatram, H. and Moon, U.K. (2014) A Time-Based Pipelined ADC Using Both Voltage and Time Domain Information. IEEE Journal of Solid-State Circuits, 49, 961-971. https://doi.org/10.1109/JSSC.2013.2293019
[10]
Xu, Y., Wu, G., Belostotski, L. and Haslett, J.W. (2016) 5-Bit 5-GS/s Noninterleaved Time-Based ADC in 65-nm CMOS for Radio-Astronomy Applications. IEEE Transactions on VLSI Systems, 24, 3513-3525.
https://doi.org/10.1109/TVLSI.2016.2558105
[11]
Wu, S.Y., Du, L., Jiang, M., Ning, N., Yu, Q. and Liu, Y. (2014) A 10-Bit 100MS/s Time Domain Flash-SAR ADC. IEEE International Conference on Electron Device and Solid-State Circuits, Chengdu, 18-20 June 2014, 1-2.
https://doi.org/10.1109/edssc.2014.7061088
[12]
Chen, Y.-J., Chang, K.-H. and Hsieh, C.-C. (2016) A 2.02–5.16 fJ/Conversion Step 10 Bit Hybrid Coarse-Fine SAR ADC with Time-Domain Quantizer in 90 nm CMOS. IEEE Journal of Solid-State Circuits, 51, 357-364.
https://doi.org/10.1109/JSSC.2015.2492781
[13]
Razavi, B. (1995) Principle of Data Conversion System Design. IEEE Press, New Jersey.
[14]
Park, M. and Perrott, M.H. (2009) A Single-Slope 80MS/s ADC Using Two-Step Time-to-Digital Conversion. IEEE International Symposium Circuits and Systems, Taipei, 24-27 May 2009, 1125-1128. https://doi.org/10.1109/iscas.2009.5117958
[15]
Wong, K.-L.-J., Rylyakov, A. and Yang, C.-K.K. (2005) A Broadband 44-GHz Frequency Divider in 90-nm CMOS. IEEE Compound Semiconductor Integrated Circuit Symposium, Palm Springs, 30 October-2 November 2005, 1-4.
[16]
Chen, L.-J. and Liu, S.-I. (2016) A 10-Bit 40-MS/s Time-Domain Two-Step ADC with Short Calibration Time. IEEE Transactions on Circuits and Systems II: Express Briefs, 63, 126-130. https://doi.org/10.1109/TCSII.2015.2483360
[17]
Sung, B.-R.-S., Jo, D.-S., Jang, Il-H., Lee, D.-S., You, Y.-S., Lee, Y.-H., Park, H.-J. and Ryu, S.-T. (2015) A 21fJ/Conversion-Step 9 ENOB 1.6GS/s 2x Time-Interleaved FATI SAR ADC with Background Offset and Timing-Skew Calibration in a 45 nm CMOS. IEEE International Solid-State Circuits Conference, San Francisco, 22-26 February 2015, 464-465.
