几种常见近似加法器的比较
Comparison of Several Common Approximate Adders

加法器作为重要的算术模块，在决定运算速度和功耗方面起着关键作用。对运算速度和效率的需求以及一些应用的容错特性促进了近似加法器的发展。传统加法器一般采用精确加法运算，电路面积、功耗均较大。近年出现了一种新兴的电路设计方法——近似加法计算，通过简化电路适当降低计算精度，最终实现面积、功耗、延时与精度的折中。本文比较了目前国内外主流的近似加法器设计，并在误差和电路特性方面进行了比较评估。仿真结果表明，LOA由于完全利用逻辑或门进行低位运算，面积最小，功耗也最小，但未考虑精度的问题，错误率最高；ETAII和ACA面积比LOA稍大，功耗也相应增加，并且设计时考虑了精度，使得错误率降低；ACA在延时方面优势最突出；SCSA配置了窗口加法器，面积与功耗更大，这也使其精度得到了更大的提升。
As an important arithmetic module, the adder plays a key role in determining the operation speed and power consumption. The demand for computing speed and efficiency and the fault tolerance of some applications have promoted the development of approximate adders. Traditional adders generally use precise addition operations, and the circuit area and power consumption are relatively large. In recent years, a new circuit design method—approximate addition calculation, has appeared. By simplifying the circuit, the calculation accuracy is appropriately reduced, and finally the area, power consumption, delay and accuracy are compromised. This article compares the current mainstream approximate adder designs at home and abroad, and compares and evaluates the errors and circuit characteristics. The simulation results show that the LOA has the smallest area and the lowest power consumption due to the full use of logic or gates for low-bit operations, but the accuracy is not considered, and the error rate is the highest; ETAII and ACA have a slightly larger area than LOA, and the power consumption increases accordingly, and accuracy is considered in the design, which reduces the error rate; ACA has the most prominent advantage in terms of delay; SCSA is equipped with a window adder, which has a larger area and power consumption, which also improves its accuracy.