DG-MOSFETs are the most widely explored device
architectures for nano-scale CMOS circuit design in
sub-50 nm due to the improved subthreshold slope and the reduced leakage power compared to bulk MOSFETs. In thin-film
(tsi < 10 nm) DG-MOS
structures, charge carriers are affected bytsi-induced
quantum confinement along with the confinement caused by a very
high electric field at the interface. Therefore, quantum confinement effects on
the device characteristics are also quite important and it needs to be incorporated along with short channel effects for
nano-scale circuit design. In thispaper, we analyzed a DG-MOSFET structure at the
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