With the need to improvement of speed of operation and the demand of low power MOSFET size scales down,?in this paper, a 50 nm gate length n-type doped channel MOS (NMOS) is simulated using ATLAS packages of Silvaco TCAD Tool so as to observe various electrical parameters at this gate length. The parameters under investigation are the threshold voltage, subthreshold slope, on-state current, leakage current and drain induced barrier lowering (DIBL) by varying channel doping concentration, drain and source doping concentration and gate oxide thickness.
References
[1]
Rahou, F.Z., Guen-Bouazza, A. and Rahou, M. (2013) Electrical Characteristics Comparison between Fully-Depleted SOI MOSFET and Partially-Depleted SOI MOSFET Using Silvaco Software. Global Journal of Researches in Engineering Electrical and Electronics Engineering, 13, 1-6.
[2]
Husaini, Y., Ismail, M.H., Zoolfakar, A.S. and Khairudin, N. (2010) Electrical Characteristics Comparison between Partially-Depleted SOI and N-MOS Devices Investigation using Silvaco. 2010 IEEE Symposium on Industrial Electronics and Applications, Penang, 3-5 October 2005, 532-536.
https://doi.org/10.1109/ISIEA.2010.5679408
[3]
Bowden, M.J. (2004) Moore’ s Law and the Technology S-Curve. SATM.
Bohr, M. (2007) A 30 Year Retrospective on Dennard’s MOSFET Scaling Paper. IEEE Solid-State Circuits Society Newsletter, 12, 11-13.
https://doi.org/10.1109/N-SSC.2007.4785534
[7]
Razavi, B. (2001) Design of Analog CMOS Integrated Circuits. McGraw-Hill, Boston, MA.
[8]
Anderson, B.L and Anderson, R.L. (2005) Fundamentals of Semiconductor Devices. McGraw-Hill Higher Education, Boston.
[9]
Silvaco International (2004) ATLAS User’s Manual Device Simulation Software. Santa Clara, Calif.
[10]
Verma, A., Mishra, A., Singh, A. and Agrawal, A. (2014) Effect of Threshold Voltage on Various CMOS Performance Parameter. International Journal of Engineering Research and Applications, 4, 21-28.
[11]
Vandana, B. (2013) Study of Floating Body Effect in SOI Technology. International Journal of Modern Engineering Research, 3, 1817-1824.
[12]
Cristoloveanu, S. and Li, S. (2014) Electrical Characterization of Silicon-on-Insulator Materials and Devices. Springer US.
[13]
Singh, S.K., Kaushik, B.K., Chauhan, D.S. and Kumar, S. (2013) Reduction of Subthreshold Leakage Current in MOS. Transistors. World Applied Sciences Journal, 25, 446-450.