Impacto de la memoria cache en la aceleración de la ejecución de algoritmo de detección de rostros en sistemas empotrados

the impact of cache memory over the speed up of viola-jones face detection algorithm on a fpga embedded processing system based in microblaze processor is analyzed in this paper. the viola-jones face detection algorithm is exposed and its software implementation is described, analyzing its main functions and data locality. the impact of size (among 2 and 16 kb) and line-length (between 4 and 8 words) of code and data cache memories are analyzed. using a spartan3a starter kit board, based on xc3s700a spartan3a fpga, with microblaze processor running at 62,5 mhz and 64mb of ddr2 external memory running at 125 mhz, code cache shows a higher impact than data cache, with optimal values of 8kb for code cache and among 4 to 16kb for data cache. a speed-up of 17 times over external memory execution of the algorithm is achieved with these cache memories sizes. cache line-length has little influence over the speed up of the algorithm.