Dise？o de un ASIC Sintetizador Digital Directo de alta velocidad

this paper describes the ip module general design process for application specific integrated circuit, intended for quasi-sine wave generation, using direct digital synthesis technique. the process was carried out in three stages: the design of direct digital synthesizer employing vhdl hardware description language, under ise design platform from xilinx. the ise platform allows to control all aspects of vhdl to fpga layout translation flow. during this stage, four of the five ip module versions designed with different features and functionalities were registered at the national copyright center (cenda). vhdl design modeling and implementation on fpga platform, for functional ip module validation, employing a spartan3e starter kit and ml507 evaluation platform from xilinx. a cmos 0.35ìm foundry technology process design adaptation, throughout some unpublished approaches based on digital circuit optimization principles that enable specific manufacturer′s technology adaptation of the design. two versions of ip module and other five technical reports have been submitted to the asic manufacturer.