Effect of Bi2Ti2O7 Seeding Layer on Capacitance-voltage Properties of Bi3:54Nd0:46Ti3O12 Films

Au/Bi3:54Nd0:46Ti3O12/Bi2Ti2O7/Si structure has been fabricated with a preferentially (111)-orientated Bi2Ti2O7 seeding layer as a ferroelectric gate of metal-ferroelectric-insulator ˉeld e ect transistor. Bi3:54Nd0:46Ti3O12 and Bi3:54Nd0:46Ti3O12/Bi2Ti2O7 ˉlms are both well-crystallized when annealed at 680±C for 40 min, and have smooth, dense and crack-free surfaces. The width of memory window of the ferroelectric gate increases with increasing electric ˉeld applied to the Bi3:54Nd0:46Ti3O12 thin ˉlms. The width of memory window of Au/Bi3:54Nd0:46Ti3O12/Bi2Ti2O7/Si with seeding layer is relatively wider than that of Au/Bi3:54Nd0:46Ti3O12/Si at the same bias voltage, and the counterclockwise hysteresis curve of Au/Bi3:54Nd0:46Ti3O12/Bi2Ti2O7/Si is referred to as polarization type switching at di erent voltages. Bi2Ti2O7 seeding layer plays an important role in alleviating the element interdi usion between Bi3:54Nd0:46Ti3O12 and Si.