FPGA Based Cost Efficient Fir Filter Using Factored CSD Technique

In this paper, an FPGA based area and power efficient FIR filter for wireless communication systems is presented. The implementation is based on Factored Canonic signed digit (FCSD) which eliminates the use of embedded multipliers. The proposed FIR filter has been implemented using Equiripple Symmetric structure on an FPGA. The developed FIR filter has been optimized in terms of MAC operation using symmetric structure. The symmetric structure requires less hardware for implementation as compared to transposed structure and also reduces hardware complexity. The performance of both symmetric and transposed structure is almost same but implementation cost varies significantly. A 20 tap FIR filter has been designed and simulated using 16 bit input and output precision with the help of Matlab. Factored Canonic signed digit (FCSD) approach is used to implement an FIR Filter taking optimal advantage of the look up table structure of FPGA. The behavioural simulation of proposed VHDL model has been performed using Modelsim simulator. The simulated model has been synthesized using Xilinx synthesis tool (XST) on Virtex 2 based xc2v3000-4ff1152 target FPGA device. The results show that symmetric FIR filter require 52.3 % less hardware as compare to transposed FIR structure. The developed symmetric FIR structure can operated at a maximum frequency of 45 MHz by consuming 6% slices, 2% flip flops and 5% Look up tables (LUTs) to provide cost effective solution for Digital Signal Processing Applications.