A Study of Energy-Area Tradeoffs of Various Architectural Styles for Routing Inputs in a Domain Specific Reconfigurable Fabric

Coarse-grained reconfigurable fabrics (CGRF’s) havegreat promise for achieving low-energy flexibledesigns for an application domain. However a universally accepted architecture for coarse-grainedreconfigurable fabrics has not yet crystallized, and many architectural options are still un- derconsideration by the research and industry community. One scientific question is how to efficientlyrouteinputs through a CGRF. This paper addresses this question in part by exploring various alternative inputsolu- tions for a stripe-based fabric. Alternativearchitectural styles examined in this paper include (i)integrated constants (IC) approach where constantsare loaded in the registers local to the functionalunits; (ii) inputs coming from the side (ICS) where both constants and variable inputs can be routedto thestripe directly where needed; (iii) ICS with extended vertical interconnect (ICS-EV); and (iv) acombination of dedicated pass gates (DPs) with standard, IC, ICS, and ICS-EV architecture styles. Weimplemented these architecture styles using 90 nm ASIC process from Synopsys. We perform a detailedarea and energy analysis on these architectures andpresent quantitative results in this paper. We observedthat the fabric with ICS and 50% DPs is the best among these options, providing 31% energy savings and62% area savings over a baseline architecture for our benchmark set.