In a preceding paper Carlos E. Saavedra, 2005, established that frequency division can be achieved with the use of inverter rings and transmission gates. In this paper, we suggest three modified circuits which obtain the similar function, namely, using Current Sink Inverter, Current Source Inverter, and Modified Current Source Inverter. The performances of the proposed circuits are examined using Cadence and the model parameters of a 45？nm CMOS process. The simulation results of the three circuits are presented and are compared. We also present the results of a simple but effective novel technique to reduce clock skew between real and complementary clock signals and the corresponding improvement achieved in maximum frequency of operation. One of the proposed circuits can operate at up to 8.2？GHz input while performing a divide-by-4 operation. 1. Introduction A frequency divider, also called, a prescaler, is a circuit that takes an input signal of a frequency, , and generates an output signal of a frequency, , such that , where is an integer. Thus when a periodic signal is given as input, frequency dividers generate a periodic signal as output at a frequency that is a fraction of the input signal. Frequency dividers are a combination of RF IC and microwave circuits. They are of particular importance to phase locked loops (PLLs). PLLs employ frequency dividers in their feedback path which divide the output frequency down to a fraction. This divided frequency is then compared with the reference frequency obtained from a crystal oscillator in a phase detector. Finally, this output phase difference tunes the VCO output voltage [1, 2]. Besides PLLs, frequency dividers are used in frequency synthesizers, phase shift keying demodulators, and so forth. One of the most recent applications of frequency dividers is applied on high speed Serializers/Deserializers (SerDes) and high frequency Local Multipoint Distribution Service (LMDS) technology. Frequency dividers can be devised with both analog and digital circuits. But as of now most of the analog frequency dividers are solely employed for EHF (>30？GHz) band. The use of digital circuits suffices for lower frequencies. Interestingly these can support both analog, and digital inputs. But digital circuits do have the drawback of increased circuit delay and speed degradation as the supply voltage is reduced and operating speed is increased. This is attributed by an increase in output RC time constant due to a reduction in gate to source driving voltage [3]. The analog approach involves several methods. The very first
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