Selected Papers from the Symposium on Integrated Circuits and Systems Design (SBCCI 2011)

SBCCI is an international forum dedicated to Integrated Circuits and Systems Design, Test and CAD, held annually in Brazil, copromoted by SBC, SBMicro, IEEE CAS, ACM SIGDA, and IFIP WG 10.5. The 24th edition of the Symposium on Integrated Circuits and Systems Design (SBCCI) was held in Jo？o Pessoa, PB, Brazil, from August 30 to September 2, 2011. Track 2.1 of SBCCI 2011 was dedicated to Reconfigurable Computing. Some of the papers of this track have been selected for this special issue. This special issue presents some of the latest developments in the area of design, specification, and modeling languages and applications of reconfigurable computing; reconfigurable architectures and novel applications of FPGAs; hardware-software codesign and coverification; emulation and prototyping techniques. Ten articles are in this issue. The main disadvantages of the reconfigurable approaches are still the costs in area and power consumption. In “HoneyComb: an application-driven online adaptive reconfigurable hardware architecture,” A. Thomas et al. present a solution for application driven adaptation of a reconfigurable architecture at register transfer level to reduce the resource requirements and power consumption while keeping the flexibility and performance for a predefined set of applications. A prototype chip of this architecture designed in 90？nm standard cell technology manufactured by TSMC is presented. Multiprocessor system-on-chip (MPSoC) security is becoming an important requirement. The challenge is to provide MPSoC security that makes possible a trustworthy system that meets the performance and security requirements of all the applications. The network-on-chip (NoC) can be used to efficiently incorporate security. In “QoSS hierarchical NoC-based architecture for MPSoC dynamic protection,” J. Sepulveda et al. propose the implementation of Quality of Security Service to overcome present MPSoC vulnerabilities. The paper presents the implementation of a layered dynamic security NoC architecture to overcome actual MPSoC vulnerabilities. Networked multiprocessor system-on-chips are used to implement novel embedded applications characterized by increasing requirements on processing performance as well as the demand for communication between several devices. Such systems require a detailed exploration on both, architectures and system design. In “Efficient execution of networked MPSoC models by exploiting multiple platform levels,” C. Roth et al. present a methodology that embeds previous work into a simulation platform, which facilitates efficient execution