Selected Papers from the 2011 International Conference on Reconfigurable Computing and FPGAs (ReConFig 2011)

The seventh edition of the International Conference on Reconfigurable Computing and FPGAs (ReConFig 2011) was held in Cancun, Mexico, from November 30 to December 2, 2011. This special issue covers actual and future trends on reconfigurable computing and FPGA technology given by academic and industrial specialists from all over the world. All papers in this special issue are extended versions of selected papers presented at ReConFig 2011, for final publication they were peer-reviewed to ensure that they are presented with the breadth and depth expected from this high-quality journal. There are a total of 11 papers in this issue. The following 4 papers correspond to the track titled General sessions. In “Analysis of fast radix-10 digit recurrence algorithms for fixed-point and floating-point dividers on FPGAs,” M. Baesler and S. O. Voigt present five different radix-10 digit recurrence dividers for FPGA architectures. All five architectures apply a radix-10 digit recurrence algorithm but differ in the quotient digit selection (QDS) function. In “Runtime scheduling, allocation and execution of real-time hardware tasks onto Xilinx FPGAs subject to fault occurrence,” Iturbe et al. present describes a novel way to exploit the computation capabilities delivered by modern field-programmable gate Arrays (FPGAs), not only towards a higher performance, but also towards an improved reliability. Computation-specific pieces of circuitry are dynamically scheduled and allocated to different resources on the chip based on a set of novel algorithms which are described in detail. In “Object recognition and pose estimation on embedded hardware: SURF-based system designs accelerated by FPGA Logic,” Schaeferling et al. describe two embedded systems for object detection and pose estimation using sophisticated point features. The feature detection step of the Speeded-Up Robust Features (SURF) algorithm is accelerated by a special IP core. The first system performs object detection and is completely implemented in a single medium-size Virtex-5 FPGA. The second system is an augmented reality platform, which consists of an ARM-based microcontroller and intelligent FPGA-based cameras which support the main system. In “Adaptive multiclient network-on-chip memory core: hardware architecture, software abstraction layer and application exploration,” D. G？hringer et al. present the hardware architecture and the software abstraction layer of an adaptive multiclient Network-on-Chip (NoC) memory core. The advantages of the novel memory core in terms of performance, flexibility, and