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电子学报  2015 

基于对偶逻辑的混合极性RM电路极性转换和优化方法

DOI: 10.3969/j.issn.0372-2112.2015.01.013, PP. 79-85

Keywords: RM电路,混合极性,逻辑综合,对偶逻辑,极性转换,极性优化

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Abstract:

针对混合极性RM(Reed-Muller)电路逻辑综合中的极性转换和极性优化问题,提出了基于对偶逻辑的极性转换和极性优化方法.从理论上证明了所提出方法的正确性,并用实验验证了其有效性和可行性.所提出方法有助于将较成熟的MPRM(Mixed-PolarityRM)极性转换和极性优化方法应用于MPDRM(Mixed-PolarityDualformofRM).对15个基于XOR的MCNC电路进行逻辑综合然后映射到FPGA(FieldProgrammableGateArray)的实验结果表明,从平均结果来看,与逻辑综合工具Espresso以及ABC的结果相比,混合极性RM电路能够获得面积和延时的优势,并且MPDRM电路极性优化结果能够得到最为优化的FPGA实现.

References

[1]  Al-Jassani B A,Urquhart N,Almaini A E A.Manipulation and optimisation techniques for Boolean logic[J].IET Computers and Digital Techniques,2010,4(3):227-239.
[2]  Green D H.Dual forms of Reed-Muller expansions[J].IEE Proceedings:Computer and Digital Techniques,1994,141(3):184-192.
[3]  卜登立,江建慧.使用系数矩阵变换极性转换的MPRM电路面积优化[J].计算机辅助设计与图形学学报,2013,25(1):126-135. Bu D L,Jiang J H.Area optimization of MPRM circuits utilizing coefficient matrix transformation based polarity conversion[J].Journal of Computer-Aided Design and Computer Graphics,2013,25(1):126-135.(in Chinese)
[4]  Rahaman H,Das D K,Bhattacharya B B.Testable design of AND-EXOR logic networks with universal test sets[J].Computers and Electrical Engineering,2009,35(5):644-658.
[5]  Mathew J,Jabir A M,Rahaman H,et al.Single error correctable bit parallel multipliers over GF(2^m)[J].IET Computers and Digital Techniques,2009,3(3):281-288.
[6]  Falkowski B J.Compact representations of logic functions for lossless compression of grey-scale images[J].IEE Proceedings:Computers and Digital Techniques,2004,151(3):221-230.
[7]  Yang M,Wang L,Tong J R,et al.Techniques for dual forms of Reed-Muller expansion conversion[J].Integration,the VLSI Journal,2008,41(1):113-122.
[8]  汪鹏君,李辉,吴文晋,等.量子遗传算法在多输出Reed-Muller逻辑电路最佳极性搜索中的应用[J].电子学报,2010,38(5):1058-1063. Wang P J,Li H,Wu W J,et al.Application of quantum genetic algorithm in searching for best polarity of multi-output Reed-Muller logic circuits[J].Acta Electronica Sinica,2010,38(5):1058-1063.(in Chinese)
[9]  Zhang H,Wang P,Gu X.Area optimization of fixed-polarity Reed-Muller circuits based on niche genetic algorithm[J].Chinese Journal of Electronics,2011,20(1):27-30.
[10]  Wang P,Li H.Low power mapping for AND/XOR circuits and its application in searching the best mixed-polarity[J].Journal of Semiconductors,2011,32(2):108-113.
[11]  汪鹏君,汪迪生,蒋志迪,等.基于PSGA算法的ISFPRM电路面积与功耗优化[J].电子学报,2013,41(8):1542-1548. Wang P J,Wang D S,Jiang Z D,et al.Area and power optimization of ISFPRM circuits based on PSGA algorithm[J].Acta Electronica Sinica,2013,41(8):1542-1548.(in Chinese)
[12]  Wang L,Almaini A E A.Exact minimisation of large multiple output FPRM functions[J].IEE Proceedings:Computers and Digital Techniques,2002,149(5):203-212.
[13]  Berkeley Logic Synthesis and Verification Group.ABC:A System for Sequential Synthesis and Verification[OL].http://www.eecs.berkeley.edu/~alanmi/abc/,2012-9-20.
[14]  Crama Y,Hammer P L.Boolean Functions:Theory,Algorithms,and Applications[M].New York:Cambridge University Press.2011.3-66.
[15]  Pang Y,Radecka K,Zilic Z.Optimization of imprecise circuits represented by Taylor series and real-valued polynomials[J].IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems,2010,29(8):1177-1190.
[16]  Hachtel G D,Somenzi F.Logic Synthesis and Verification Algorithms[M].New York:Kluwer Academic Publishers.2002.127-184.
[17]  卜登立,江建慧.基于混合多值离散粒子群优化的混合极性Reed-Muller最小化算法[J].电子与信息学报,2013,35(2):361-367. Bu D L,Jiang J H.Hybrid multi-valued discrete particle swarm optimization algorithm for mixed-polarity Reed-Muller minimization[J].Journal of Electronics and Information Technology,2013,35(2):361-367.(in Chinese)
[18]  Yang S.Logic Synthesis and Optimization Benchmarks User Guide Version 3.0[R].Microelectronics Center of North Carolina,Research Triangle Park,NC,1991.

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