Jain M K,Balakrishnan M,Kumar A.ASIP design methodologies:survey and issues[A].Proceeding of 14th International Conference on VLSI Design[C].Los Alamitos,CA:IEEE Computer Society,2001.76-81.
[2]
Galuzzi C,Bertels K.The instruction-set extension problem:a survey[J].ACM Transactions on Reconfigurable Technology and Systems,2011,4(2):1-28.
[3]
Barat F,Lauwereins R.Reconfigurable instruction set processors:a survey[A].Proceedings of 11th International Workshop on Rapid System Prototyping[C].Los Alamitos,CA:IEEE Computer Society,2000.168-173.
[4]
Vasicek Z,Sekanina L.An evolvable hardware system in Xilinx Virtex II Pro FPGA[J].International Journal of Innovative Computing and Applications,2007,1(1):63-73.
[5]
Lewis D,et al.The Stratix II logic and routing architecture[A].Proceedings of 13th International Symposium on Field-Programmable Gate Arrays[C].New York:ACM,2005.14-20.
[6]
Li X,Yang H,Zhong H.Use of VPR in design of FPGA architecture[A].Proceedings of 8th International Conference on Solid-State and Integrated Circuit Technology[C].Shanghai:IEEE Press,2006.1880-1882.
[7]
Lagadec L,Pottier B.Object-oriented meta tools for reconfigurable architectures[A].Proceedings of 2000 International Conference on Modeling,Signal Processing and Control[C].Bellingham WA:SPIE,2000.69-79.
[8]
Bossuet L,Gogniat G,et al.A modeling method for reconfigurable architectures[A].Proceedings of 2nd International Workshop on System-on-Chip for Real-Time Applications[C].Alberta,Canada:IEEE Computer Society,2002.170-179.
[9]
Li Z,et al.A modeling and mapping method for coarse/fine mixed-grained reconfigurable architecture[A].Proceedings of 11th International Conference on Solid-State and Integrated Circuit Technology[C].Xi''an:IEEE Press,2012.1-4.
[10]
Ito K.A scheduling and allocation method to reduce data transfer time by dynamic reconfiguration[A].Proceedings of 2000 Asia and South Pacific Design Automation Conference[C].New York:ACM,2000.323-328.
[11]
Eguro K.Resource allocation for coarse-grain FPGA development[J].IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems,2006,24(10):1572-1581.
[12]
Plaxton C G,Yu S,et al.Reconfigurable resource scheduling[A].Proceedings of 18th Annual ACM Symposium on Parallelism in Algorithms and Architectures[C].New York:ACM,2006.93-102.
[13]
Cavrilovska A,Kumar S,et al.High-performance hypervisor architectures:virtualization in HPC systems[A].Proceedings of 1st Workshop on System-Level Virtualization for High Performance Computing[C].New York:ACM,2007.1-8.
[14]
Shafigue M,Bauer L,et al.Minority-game-based resource allocation for run-time reconfigurable multi-core processors[A].Proceedings of 2011 Design,Automation & Test in Europe[C].New York:ACM,2011.1-6.
[15]
Li J,Das A,Kumar A.A design flow for partially reconfigurable heterogeneous multi-processor platforms[A].Proceedings of 23rd IEEE International Symposium on Rapid System Prototyping[C].Tampere,Finland:IEEE Reliability Society,2012.170-176.
[16]
齐骥,李曦,等.基于硬件任务顶点的可重构系统资源管理算法[J].电子学报,2006,34(11):2094-2098. Qi Ji,Li Xi,et al.Algorithms ofresource management for reconfigurable systems based on hardware task vertexes[J].Acta Electronica Sinica,34(11):2094-2098.(in Chinese)
[17]
周学海,等.基于差分进化和贪心策略的自定义指令选择算法研究[J].电子学报,2009,37(2):372-376. Zhou Xue-hai,et al.Study on differential evolution and greedy strategy based custom instruction selection algorithms[J].Acta Electronica Sinica,2009,37(2):372-376.(in Chinese)